In recent years, transmission speeds in interfaces increase, and a bit rate of data transmission and reception has become several Gbps (bits/second). As operation speeds of memory devices such as a DDR-SDRAM (Double Date Rate-Synchronous Dynamic Random Access Memory) have also been increased, a speed of the interface between a main circuit and the DDR-SDRAM is desired to be increased. For example, in an interface with respect to a DDR-SDRAM of which input and output operations are carried out at 2.133 Gbps, a transmission clock is 1.066 GHz since the DDR-SDRAM operates at a double data rate. However, the input and output operations are controlled by a clock of 2.133 GHz. Further, there may be an interface in which data signals of a plurality of bits are transmitted in parallel in order to increase a data rate of the interface. In such interface, a phase adjustment unit (De-Skew Unit) which cancels timing skews among data outputs of the plurality of bits is provided to adjust phases of data outputs. The embodiments relate to output circuits in which phases of data outputs are adjusted by a transmission clock.
An internal circuit operates at low speed since it is difficult to operate at high-speed. An output circuit converts parallel data of a plurality of bits to serial data of high-speed. As described above, when the interface in which data signals of a plurality of bits are transmitted in parallel is used, the output circuit includes a plurality of output blocks, in each of which N-bits (N: power of 2) parallel data is converted to 1-bit serial data. For example, when a number of output blocks is M, data signals of M-bits are transmitted in parallel. Skews among outputs of M-bits parallel data are adjusted to zero. In the adjustment of the skews, adjustment values cancelling the skews are previously measured in a training mode, and the adjustment values are stored. In normal operations, the skews are adjusted based on the stored adjustment values. Hereinafter, a plurality of output blocks for transmitting M-bits parallel data are referred as “output blocks of M-bits”.
When the transmission speed increases as described above, skews among signals of parallel data output from the internal circuit to the output circuits and skews in signal paths from the output circuits to output terminals relatively become so large as not to be neglected. When N-bits parallel data is converted to 1-bit serial data in each of the output blocks of M-bits, 2-bits parallel data is converted to 1-bit serial data at a last stage of each output block. Stages except the last stage are circuits which operate at a frequency of the transmission clock or frequencies of clocks less than ½ thereof, and therefore, operational margins of such circuits are comparatively large. However, the last stage is a circuit which operates at a double frequency of the transmission clock. Therefore, since the phase adjustment unit in the last stage operates at a clock of high-speed frequency, consuming power of the circuit forming the last stage is large and an operational margin thereof is small.
Further, the phase adjustment units are formed by DLLs (Delay Locked Loops). Since a plurality of DLLs are respectively provided for the output circuits of M-bits, rising edges/falling edges of outputs of the DLLs do not coincide with each another.